This invention relates to digital-to-analog converters, and more particularly to a digital-to-analog converter of the type known as an interpolative decoder for decoding a linear PCM code.
An interpolative decoder is described in detail in G. R. Ritchie et al; "Interpolative Digital to Analog Converters", IEEE, COM-22, 11, November, 1974. The feature of this system consists in that the conversion of a quantized level into an analog value is not entirely realized with a ladder circuit. Instead, only a segment end is realized with a ladder circuit, and levels equally divided within a segment (hereinbelow, termed "uniformly quantized levels") are realized by time averaging operations. This brings forth the effect that the resistance precision required for the ladder resistance network is moderated considerably.
The prior-art interpolative decoder, however, has had the disadvantage that the circuit arrangement becomes complicated because the signals relating to the more significant bits and the 1-bit signals into which the signals relating to the less significant bits representative of the uniformly quantized level which are developed on a time axis are added in a digital stage. Supposing, by way of example, that it is desired to produce an interpolative decoder for receiving a signal of 12 bits in which 7 bits among the more significant 8 bits, except for 1 polarity bit, are allotted to segment select bit signals, and in which 4 bits constitute uniformly quantized bit signals to be developed on a time axis, in such case, a digital adder of 8 bits and a register for storing an added result are required. Therefore, in a case where this interpolative decoder is put into an IC, the area of the device becomes large.